Many electronic devices, such as personal computers, workstations, computer servers, mainframes and other computer related equipment such as printers, scanners and hard disk drives use memory devices that provide substantial data storage capability, while incurring low power consumption. One type of memory device that is well-suited for use in the foregoing devices is the dynamic random access memory (DRAM).
Briefly, and in general terms, a DRAM includes a memory array having a plurality of memory cells that can be arranged in rows and columns. A plurality of conductive word lines may be positioned along the rows of the array to couple cells in respective rows, while a plurality of conductive bit lines may be positioned along columns of the array and coupled to cells in the respective columns. The memory cells in the array may include an access device, such as a MOSFET device, and a storage device, such as a capacitor. The access device and the storage device may be operably coupled so that information is stored within a memory cell by imposing a predetermined charge state (corresponding to a selected logic level) on the storage device, and retrieved by accessing the charge state through the access device. Since the charge state in the storage device typically dissipates due to leakage from the cell, the storage device within each memory cell may be periodically refreshed. Current leakage from the cells in the DRAM may occur along several different paths, and if the current leakage is excessive, then the cell refresh interval may be relatively short, which can adversely affect access time for the memory device, and increase the amount of power consumed.
As the cell density of memory devices increases, access devices that are vertically disposed in a supporting substrate are increasingly favored. In general, the vertical access device may be formed in a recess having opposing vertical sidewalls and a horizontal floor extending between the sidewalls. A dielectric layer may then be disposed in the recess, and a gate structure applied. Doped regions may then be formed in the structure to create active (source and drain) regions. Although the vertical access device has a reduced footprint when compared to a laterally-disposed access device, additional difficulties may be introduced. For example, the vertical access device may introduce higher overlap capacitances, and can be subject to higher gate-induced drain leakage (GIDL) currents in the vicinity of the overlap region. GIDL current in the overlap region may be caused by band to band tunneling effects, and can impose significant operating limitations on thin-oxide vertical access devices. Since the tunneling current may be generally exponentially dependent on the electric field present in the active region, small variations in the doping of the active region and/or the oxide thickness in the vertical access device can adversely affect GIDL current.
What is needed in the art are access structures that have the potential to reduce the adverse effects of GIDL currents. Additionally, there is a need in the art for memory devices having improved retention times and lower power consumption.